Die architecture accommodating high-speed semiconductor devices

ABSTRACT

In a semiconductor memory device, a die architecture is provided that arranges memory arrays into a long, narrow configuration. Bond pads may then be placed along a long side of a correspondingly shaped die. As a result, this architecture is compatible with short lead frame “fingers” for use with wide data busses as part of high speed, multiple band memory integrated circuits.

TECHNICAL FIELD

[0001] This invention relates generally to semiconductor devices. Inparticular, this invention relates to die architecture for semiconductormemory devices configured to execute high speed applications, such asthose performed in synchronous dynamic random access memory devices.

BACKGROUND OF THE INVENTION

[0002] Assembling an integrated circuit package often involves attachinga die to a lead frame. As an additional part of assembly, bond wires areused to electrically connect the conductive leads of the lead frame tothe die's bond pads. The die/lead frame assembly is then encased in ahousing with the outer ends of the conductive leads remaining exposed inorder to allow electrical communication with external circuitry. Thedie's architecture may represent one of many circuitry configurations,such as a Dynamic Random Access Memory (DRAM) circuit or, morespecifically, a synchronous DRAM (SDRAM) circuit.

[0003] The high speed synchronous operations associated with SDRAMcircuitry often involve communication with an external device such as adata bus. Occasionally, the data bus may be relatively wide incomparison to the standard width of prior art SDRAM dies. The width ofthe data bus, in turn, requires an appropriate number of conductiveleads positioned to accommodate the bus. Further, the position of theconductive leads and their spacing limitations require a certain amountof die space for bond pad connection. However, the prior art does notprovide a die having one particular region that can provide enough bondpads to accommodate all of the conductive leads. Rather, thearchitecture of the die as found in prior art allows for bond pads to belocated in different areas of the die. Consequently, conductive leads ofdifferent lengths are needed to connect the bond pads to the relativelywide data bus. These differing lengths slow the operations of the SDRAM,or any semiconductor device for that matter, as it takes longer forsignals to travel through the longer conductive leads. Thus, ifsynchronized signals are desired, the speed of the device is limited bythe speed of signal propagation through the longest conductive lead. Thelonger leads also have a greater inductance associated with them,thereby further slowing signal propagation. Moreover, the inductance inthe longer conductive leads is different from the inductance associatedwith the relatively short conductive leads. This imbalance in inductionmakes synchronizing the signals even more difficult.

[0004] Thus, it would benefit the art to have a die configuration thatprovides bond pads in a common location such that all of the conductiveleads of the lead frame could be the same length. It would furtherbenefit the art if the die configuration allowed uniformly shortconductive leads. Indeed, this desire is mentioned in U.S. Pat. No.5,408,129, by Farmwald, et al., which discloses a high-speed bus as wellas memory devices that are adapted to use the bus. Specifically,Farmwald '129 discloses a narrow multiplexed bus, as demonstrated byFarmwald's preferred embodiment, wherein the bus comprises only nine buslines. Accordingly, Farmwald's narrow bus allows for a relatively lownumber of bond pads on the die of a memory device. Farmwald '129concludes that it would be preferable to place the small number of bondpads on one edge of each die, as that would allow for short conductiveleads. Farmwald '129 at col. 18, In. 37-43. However, it is possible todo so under Farmwald '129 only because the “pin count . . . can be keptquite small” due to the narrow architecture of the bus. Id. at In.17-18.

[0005] Contrary to the teachings in Farmwald '129, it would beadvantageous at times to accommodate a relatively wide bus requiring alarge number of pins. It would therefore be additionally advantageous toprovide a die capable of providing the correspondingly large number ofbond pads on one side of the die.

SUMMARY OF THE INVENTION

[0006] Accordingly, the present invention provides die architecturesallowing for the relocation of the die's bond pads. One embodiment ofthis invention arranges for all of the die's bond pads to be located onone side of the die, with the corresponding memory banks arrangedaccordingly. In a preferred embodiment, the length of the die sidehaving the bond pads is extended relative to prior architectures and thememory arrays are shaped to follow along the extended side.Consequently, the perpendicular sides contiguous to the extended sidemay be shortened. This architecture has the advantage of allowing thedie to cooperate with a lead frame having conductive leads of the samelength, thereby balancing inductance and aiding in the ability tosynchronize signals. This architecture also has the advantage ofallowing the conductive leads to be relatively short, which furtherincreases the operational speed of the die's circuitry and decreasesinductance.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007]FIG. 1 depicts the architecture of a SDRAM chip as found in theprior art.

[0008]FIG. 2 illustrates an SDRAM chip within a lead frame as found inthe prior art.

[0009]FIGS. 3a and 3 b portray a first exemplary embodiment of thepresent invention.

[0010]FIG. 4 represents an embodiment of the present invention incooperation with a lead frame.

[0011]FIGS. 5a and 5 b demonstrate a second exemplary embodiment of thepresent invention.

[0012]FIGS. 5c and 5 d illustrate a third exemplary embodiment of thepresent invention.

[0013]FIGS. 6a and 6 b depict a fourth exemplary embodiment of thepresent invention.

[0014]FIGS. 6c and 6 d depict a fifth exemplary embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0015]FIG. 1 depicts the architecture of an SDRAM 20 as it exists in theprior art. The SDRAM 20 is fabricated on a die 22 and includes sixteenmemory banks B0 through B15. The shape of each bank is determined by thenumber and arrangement of component sub-arrays. In this prior artexample, each bank comprises a row of sixteen sub-arrays. Bank B0, forexample, comprises sub-arrays 000 through 015. Similarly, bank B1comprises sub-arrays 100 through 115. For purposes of explaining thecurrent invention, it is understood that each bank is analogouslynumbered, ending with sub-arrays 1500 through 1515 comprising memorybank B15. Each sub-array contains a number of memory bit components andaccompanying n/p channel sense amplifier circuitry 26 as well as rowdecoder circuitry 28. The banks B0-B15 are also serviced by a first 64xDC sense amp 30 and a second 64x DC sense amp 32. It should be notedthat the size and number of DC sense amps can vary based on thecompression rate desired. Column decoder circuitry 34 is located next tothe DC sense amps 30 and 32; and a column select line 36 extends fromthe column decoder circuitry 34 through all of the memory banks B0-B15.Logic circuitry is located in a region 38 on the other side of the DCsense amps 30 and 32 relative to the memory banks B0-B15. Bond pads 40are placed on the perimeter of the die 22 to allow easy access. Forpurposes of this application, the term “bond pad” includes anyconductive surface configured to permit temporary or permanentelectrical communication with a circuit or node. Further, it should benoted that there exists a series of bond pads—defined here as accesspads, wherein each access pad of the series is coupled to one sub-arrayof each bank, thereby allowing electrical signals to access thosesub-arrays. For example, access pad 40A is defined to be coupled tosub-arrays 000, 100, 200, 300, 400, through 1500. Access pad 40G iscoupled to sub-arrays 006 through 1506. Access pad 40P, in turn, isdefined to be coupled to sub-arrays 015 through 1515. Accordingly, thereare thirteen other access pads, each associated with a correspondingcolumn comprising one sub-array from every bank. In order to keepconnective circuitry to a minimum, these sixteen access pads are locatednear their respective sub-arrays. It should be noted that, in FIG. 1,the group of sub-arrays 000 through 1500 is highlighted in bold forpurposes of indicating the common association those sub-arrays have witha particular access pad (such as 40A, for these sub-arrays). Groups006-1506 and 015-1515 are similarly highlighted. Other bond pads 40,representing additional input and output terminals for communicatingwith the die 22, are placed in the remaining available spaces on the die22, which may include more than one side of the die 22.

[0016] Packaging of the die 22 may be influenced by the fact that theinternal circuitry of the die 22 will be interacting with a data bus.Specifically, as seen in FIG. 2, the die 22 can be placed within a leadframe wherein the conductive leads 48, 50 extend from the die 22 andeventually orient in one direction in anticipation of connecting to thedata bus. In FIG. 2, bond pads 40 that are on the die's near side 42—theside that will be closest to the external device—require only relativelyshort conductive leads 48. However, bond pads 40 along the sides 44, 46contiguous to the near side 42 require longer conductive leads 50.Assuming that the signal propagation rate through the conductive leads48, 50 is generally the same, the longer conductive leads 50 will take alonger time to transmit any signals. Moreover, inductance of the longerconductive leads 50 will be greater than inductance of the shorterconductive leads 48.

[0017]FIGS. 3a and 3 b illustrate one embodiment of the currentinvention that solves these problems. In this embodiment, the memorybanks are separated into discontiguous portions. Despite placingportions of the banks in separate locations, the columnar arrangement ofsub-arrays, one from each bank, is retained, and the columns are rotatedninety degrees relative to the configuration addressed above. Thus,rather than being parallel to the contiguous sides 44 and 46, thecolumns are now parallel to the near side 42. For example, the sixteensub-arrays associated with access pad 40A (000 through 1500) extendedalong contiguous side 44 in the prior art die depicted in FIG. 1. Again,this group of sub-arrays commonly coupled to access pad 40A ishighlighted to show the new orientation of the sub-arrays and of thegroup in general. In FIG. 3a, this group of sub-arrays now extends alongthe near side 42. While this group of sub-arrays 000 through 1500 isstill relatively near contiguous side 44, this is not necessary forpurposes of the current invention; this group could occupy any of thecolumnar positions depicted in FIG. 2. Regardless of the particularposition of the columns, it is preferred that their respective accesspad remain relatively close by. Moreover, given this new configuration,each sub-array is now oriented perpendicular to the near side 42 of thedie 22.

[0018] Further, it should be noted that, while the arrangements ofsub-arrays in FIG. 2 might be described as “rows” given the ninetydegree rotation, the arrangements are referred to as “columns” or“columnar positions” for purposes of demonstrating the continuity withportions of the die architecture in FIG. 1.

[0019] As an example of this continuity, the row decoder circuitry 28and column decoder circuitry are also rotated ninety degrees and,therefore, retain their orientation relative to each sub-array. Columndecoder devices in this embodiment include a first modified columndecoder circuit 60 interposed between a 700 series of sub-arrays (700 to703) and an 800 series of sub-arrays (800-803). In addition, a firstmodified column select line 62 extends from the first modified columndecoder circuit 60 through sub-arrays 700 to 000. Similarly, a secondmodified column select line 64 extends from the first modified columndecoder circuit 60 through sub-arrays 800 to 1500. This embodiment alsoincludes three other similarly configured modified column decodercircuits 66, 61, and 67, each with their own modified column selectlines 68 and 70, 63 and 65, and 69 and 71, respectively.

[0020] Moreover, instead of two 64x DC sense amps 30 and 32, thisembodiment of the present invention uses four 32x DC sense amps 52, 54,56, and 58. However, as in the prior art, the size and number of DCsense amps merely affect data compression and no one DC sense ampconfiguration is required for any embodiment of the current invention.

[0021] In this exemplary embodiment, the columns are further arranged ingroups of four. In doing so, this embodiment partially retains some ofthe bank continuity found in the prior art. For example, the sub-arraysequence 000, 001, 002, and 003 of Bank 0 remain contiguous. The Bank 0sequence continues in the next four rotated columns with sub-arrays 004,005, 006, and 007 remaining next to each other. These intervals of bankcontinuity apply to the other memory banks as well and aid in minimizingthe complexity of row decoder and column decoder circuitry. Arrangingthe columns in groups of four also means that certain columns will befurther away from the near side 42 than other columns. As a result,there may be unassociated sub-arrays between a column and its accesspad. For example, connective circuitry (not shown) coupling column003-1503 to access pad 40D will probably pass by sub-arrays withincolumns 002-1502, 001-1501, and 000-1500.

[0022] Additionally, this arrangement of rotated columns allows foraltering the dimensions of the die 22. Not only can the near side 42 beextended to a length commensurate with the data bus, but the contiguoussides 44 and 46 may also be shortened. Moreover, extending the near side42 provides chip space for the bond pads 40 that had been along thecontiguous sides 44, 46 in the prior architecture. FIG. 4 demonstratesthe result of this architecture: when the die 22 is attached to a leadframe 76 having conductive leads on only one side, the die's formationaccommodates short conductive leads 78 of uniform length. Packaging thedie 22 with this lead frame 76, in turn, allows for fast operation ofthe die 22 in conjunction with a device having a relatively large numberof data terminals, such as a wide data bus.

[0023] Other embodiments of the present invention can lead to the samepackaging advantages. The exemplary embodiment in FIGS. 5a and 5 b, forinstance, demonstrates that, although the sub-arrays are rotated ninetydegrees as in FIGS. 3a and 3 b, it is not necessary to retain thecolumnar arrangement of the previous embodiment. Instead of the 16×1columns, the sub-arrays in FIGS. 5a and 5 b have been grouped into 4×4associations. As demonstrated in the previous embodiment, there is arepetition of the sub-array pattern at continuous intervals. In theembodiment shown in FIGS. 5a and 5 b, sequential sub-arrays of aparticular bank are separated by sub-arrays of other banks. Sub-arrays000 and 001 of Bank 0, for example, are separated by sub-arrays 400,800, and 1200. As further demonstrated in the previous embodiment, it isstill preferred to configure the access pads near their respectivegrouping. Nevertheless, because the associated sub-arrays in FIGS. 3aand 3 b extend along one dimension and include one sub-array from everybank, there is more sharing of row decoder circuitry 28 as well ascolumn select circuitry 62, 64, 68, 70, 63, 65, 69, and 71 in thatembodiment than in the more fragmented sub-array groupings depicted inFIGS. 5a and 5 b. Accordingly, the embodiment in FIGS. 3a and 3 b is themore preferred embodiment of the two. FIGS. 5c and 5 d represent analternate configuration of 4×4 associations.

[0024] There are also alternative embodiments that do not involverotating the orientation of the sub-arrays, as demonstrated in FIGS. 6aand 6 b. Whereas there are sixteen rows of sub-arrays extending backfrom the near side 42 of the die 22 in FIG. 1, the die 22 in FIGS. 6aand 6 b has a memory configuration only eight sub-arrays “deep.”Further, the sub-arrays are gathered into 8×2 groupings, again with onesub-array from every bank in each group and with each group associatedwith a particular access pad. Moreover, each group is orientedperpendicular to the near side 42 of die 22. Group 90 has been definedto contain sub-arrays 000 through 1500, group 92 contains sub-arrays 001through 1501, and group 94 contains sub-arrays 002 through 1502. Whileno particular order of groups is required, it is noteworthy in thisembodiment that the sub-arrays 800 through 1500 in group 90 are next tosub-arrays 801 through 1501 in group 92. In effect, groups 90 and 92could be considered “mirror images” of each other. This mirror imageconfiguration is useful in compressing data for test modes and inmaximizing the opportunity to share row decoder circuitry 28. It canfurther be seen in FIGS. 6a and 6 b that group 94 is a mirror image ofgroup 92, wherein sub-arrays 002 through 702 are respectively contiguousto sub-arrays 001 through 701. While these mirror image configurationsare preferable in a die architecture having 8×2 sub-array groupings,they are not necessary to realize the current invention. As in otherembodiments, this one has a die shape capable of including bond pads ina configuration accommodatable to communication with an external device,with a memory arrangement generally conforming to the die shape.

[0025] The embodiment in FIGS. 6a and 6 b also benefits from four 32x DCsense amps 80, 81, 82, and 83. Further, there are two column decodercircuits 84 and 85, each associated with respective column select lines86 and 87. Unlike the previous embodiments, however, each sub-array isoriented parallel to the near side 42 of the die 22. FIGS. 6c and 6 drepresent an alternate configuration of 8×2 associations or groupings ofsub-arrays.

[0026] One of ordinary skill can appreciate that, although specificembodiments of this invention have been described for purposes ofillustration, various modifications can be made without departing fromthe spirit and scope of the invention. For example, embodiments of diearchitecture covered by this invention need not be restricted to placingbond pads on only one side of a die. It may be desirable in certainapplications to use a lead frame having conductive leads facing two ormore sides of a die. Die architectures included within the scope of thisinvention could locate the die's bond pads to allow for conductive leadsof a uniform length and, more specifically, a uniformly short length onall relevant sides. In addition, the dimensions of the memory bankscould be adapted to conform to a particular die's requirements. If, forexample, the number of bond pads and the conductive lead pitchlimitations require a die side even longer than the near side 42 inFIGS. 5a and 5 b, the 4×4 banks of rotated sub-arrays can be replacedwith an embodiment having a series of rotated sub-arrays grouped into2×8 banks. Accordingly, the invention is not limited except as stated inthe claims.

Exhibit A

[0027] Appl. No. Atty Dkt # Applicants Filed Title 09/023,254 501083.01DonaId M. Morgan 02-13-98 DIE ARCHITECTURE ACCOMMODATING (97-0002) andTodd A. Merritt HIGH-SPEED SEMICONDUCTOR DEVICES 09/301,643 501083.02Donald M. Morgan 04-28-99 DIE ARCHITECTURE ACCOMMODATING (97-0002.01 andTodd A. Merritt HIGH-SPEED SEMICONDUCTOR DEVICES 09/439,972 501083.03Donald M. Morgan 11-12-99 DIE ARCHITECTURE ACCOMMODATING (97-0002.02)and Todd A. Merritt HIGH-SPEED SEMICONDUCTOR DEVICES 09/652,996501083.04 Donald M. Morgan 08-31-00 DIE ARCHITECTURE ACCOMMODATING(97-0002.03) and Todd A. Merritt HIGH-SPEED SEMICONDUCTOR DEVICES09/652,578 501083.05 Donald M. Morgan 08-31-00 DIE ARCHITECTUREACCOMMODATING (97-0002.04) and Todd A. Merritt HIGH-SPEED SEMICONDUCTORDEVICES 09/652,584 501083.06 Donald M. Morgan 08-31-00 DIE ARCHITECTUREACCOMMODATING (97-0002.05) and Todd A. Merritt HIGH-SPEED SEMICONDUCTORDEVICES 09/652,586 501083.07 Donald M. Morgan 08-31-00 DIE ARCHITECTUREACCOMMODATING (97-0002.06) and Todd A. Merritt HIGH-SPEED SEMICONDUCTORDEVICES 09/652,587 501083.08 Donald M. Morgan 08-31-00 DIE ARCHITECTUREACCOMMODATING (97-0002.07) and Todd A. Merritt HIGH-SPEED SEMICONDUCTORDEVICES 09/652,839 501083.09 Donald M. Morgan 08-31-00 DIE ARCHITECTUREACCOMMODATING (97-0002.08) and Todd A. Merritt HIGH-SPEED SEMICONDUCTORDEVICES Not Yet 501083.10 Donald M. Morgan 09-25-01 DIE ARCHITECTUREACCOMMODATING Assigned and Todd A. Merritt HIGH-SPEED SEMICONDUCTORDEVICES Not Yet 501083.11 Donald M. Morgan Concurrently DIE ARCHITECTUREACCOMODATING Assigned and Todd A. Merritt herewith HIGH-SPEEDSEMICONDUCTOR DEVICES

What is claimed is:
 1. A method of allowing generally synchronouscommunication between an external device and memory sub-arrays on a die,comprising: arranging said memory sub-arrays generally along a dimensionof said external device; and accommodatingly shaping said die inrelation to said memory sub-arrays.
 2. The method in claim 1, furthercomprising: providing a plurality of bond pads on said die; couplingeach sub-array to a bond pad of said plurality of bond pads; andarranging said plurality of bond pads on said die generally along saiddimension of said external device.
 3. A method of providing forelectrical communication between an external device and memory bankscomprised of sub-arrays on a die, comprising: cooperatively configuringdimensions of said die in relation to said external device; andgenerally conformably arranging said memory banks within said dimensionsof said die, further comprising: discontiguously arranging at least onesub-array in at least one memory bank in relation to other sub-arrays ofsaid one memory bank.
 4. A method of conforming a die for operation witha lead frame having lead fingers of generally equal length, comprising:providing a first memory bank comprising a first plurality ofsub-arrays; providing a second memory bank comprising a second pluralityof sub-arrays, wherein said second plurality of sub-arrays is equal innumber to said first plurality of sub-arrays; providing a plurality ofaccess pads on said die, wherein said plurality of access pads is equalin number to said first plurality of sub-arrays; associating each accesspad of said plurality of access pads with one sub-array from said firstplurality of sub-arrays and one sub-array from said second plurality ofsub-arrays; arranging one sub-array of every sub-array from said firstplurality of sub-arrays and an associated sub-array from said secondplurality of sub-arrays near a lead finger; and placing each access padbetween a lead finger and associated sub-arrays from said first andsecond plurality of sub-arrays.
 5. The method in claim 4, furthercomprising placing at least one unassociated sub-array between oneaccess pad and said associated sub-arrays.
 6. The method in claim 5,further comprising placing at most three unassociated sub-arrays betweenone access pad and associated sub-arrays from said first plurality ofsub-arrays and said second plurality of sub-arrays.
 7. A method ofconfiguring a die having a length and a depth, comprising: providing aplurality of sub-arrays on said die, said plurality of sub-arrayscomprising a first sub-array group and a second sub-array group; placingsaid first sub-array group generally entirely along said length of saiddie; placing said second sub-array group along said depth of said die;providing a plurality of bond pads on said die generally entirely alongsaid length of said die; associating proximate sub-arrays of saidplurality of sub-arrays with a particular bond pad of said plurality ofbond pads.
 8. The method in claim 7, further comprising placing bondpads next to associated sub-arrays.
 9. A method of constructing a memorycircuit, comprising: providing a plurality of memory banks on a die,further comprising providing a plurality of sub-arrays for each memorybank; providing a plurality of access pads on said die; electricallyassociating each access pad of said plurality of access pads with onesub-array from each memory bank; providing a physical separation of afirst group of sub-arrays from a second group of sub-arrays within eachmemory bank; and physically associating sub-arrays that are commonlyelectrically associated with an access pad.
 10. The method in claim 9,wherein physically associating sub-arrays further comprises establishinga number of sub-array associations equal in number to said plurality ofmemory banks.
 11. The method in claim 10, further comprising providing aplurality of bond pads on one side of said die, wherein said pluralityof access pads is a subset of said plurality of bond pads.
 12. Themethod in claim 11, further comprising physically orienting saidplurality of sub-arrays in each memory bank perpendicular to said oneside of said die.
 13. The method in claim 12, wherein physicallyassociating said sub-arrays further comprises configuringone-dimensional groupings.
 14. The method in claim 12, whereinphysically associating said sub-arrays further comprises configuringtwo-dimensional groupings.
 15. A method of configuring a die,comprising: providing a plurality of memory sub-arrays on said die;defining at least one memory bank from said memory sub-arrays; providingrow decoder circuitry and column decoder circuitry for said memory bank;and fragmenting said row decoder circuitry into a number of portionsexceeding a number of defined memory banks.
 16. The method in claim 15,wherein fragmenting said row decoder circuitry further comprisesdefining a plurality of parallel axes with portions of said row decodercircuitry.
 17. The method in claim 16, further comprising fragmentingsaid column decoder circuitry.
 18. The method in claim 17, whereindefining at least one memory bank further comprises defining a pluralityof memory banks from said plurality of memory sub-arrays; and whereinsaid method further comprises proximately positioning correspondingmemory sub-arrays of each memory bank.
 19. The method in claim 18,further comprising locationally separating some memory sub-arrays withina memory bank.
 20. A circuit configured to operate with an externaldevice, comprising: a die having a device accommodatable dimension; afirst memory bank on said die further comprising a first sub-array and asecond sub-array; a second memory bank on said die further comprising athird sub-array and a fourth sub-array; a first sub-array arrangementfurther comprising said first sub-array and said third sub-array; asecond sub-array arrangement further comprising said second sub-arrayand said fourth sub-array and aligned with said first sub-arrayarrangement along said device accommodatable dimension; a first accesspad coupled to said first sub-array arrangement; and a second access padcoupled to said second sub-array arrangement and aligned with said firstaccess pad along said device accommodatable dimension.
 21. The circuitin claim 20, wherein said first sub-array arrangement is next to saidsecond sub-array arrangement; said third sub-array is next to saidfourth sub-array; and said first sub-array is isolated from said secondsub-array.
 22. The circuit in claim 20, wherein said first sub-arrayarrangement is next to said second sub-array arrangement; said thirdsub-array is next to said fourth sub-array; and said third and fourthsub-arrays are interposed between said first and second sub-arrays. 23.A memory array, comprising: a plurality of memory banks on a die,wherein each memory bank further comprises a plurality of sub-arrays anda first portion of said plurality of sub-arrays for each memory bank isphysically isolated from a second portion of said plurality ofsub-arrays; and a plurality of access pads on one side of said die,wherein each access pad is coupled to one sub-array from every memorybank; and wherein a sub-array coupled to an access pad is generallyproximate to other sub-arrays coupled to said access pad, all of saidsub-arrays coupled to one access pad defining a particular sub-arraygroup.
 24. The memory array of claim 23, wherein said plurality ofsub-arrays have an orientation parallel with said one side of said die.25. The memory array of claim 24, wherein each particular sub-arraygroup comprises at least two sub-arrays aligned along said one side ofsaid die.
 26. The memory array of claim 25, wherein a sub-array of onesub-array group is in the same bank as a contiguous sub-array in anothersub-array group.
 27. The memory array of claim 25, wherein a particularsub-array group is aligned perpendicular to said one side of said die.28. A memory system, comprising: a die; a plurality of memory banks onsaid die; a plurality of bond pads on one side of said die; and columnselect circuitry on said die defining an axis generally parallel to saidplurality of bond pads and passing through every memory bank of saidplurality of memory banks.
 29. The memory system of claim 28, furthercomprising column decoder circuitry coupled to said column selectcircuitry and oriented generally perpendicular to said column selectcircuitry.
 30. A packaged integrated circuit configured to communicatewith an external device having a plurality of data terminals,comprising: a lead frame having a plurality of conductive leadsgenerally corresponding to said plurality of data terminals; a dieattached to said lead frame and further comprising: a plurality ofdiscontiguous memory banks on said die generally conformal to dimensionsof said die, and a plurality of bond pads generally corresponding tosaid plurality of conductive leads and coupled to said plurality ofdiscontiguous memory banks; and a plurality of bond wires connectingsaid plurality of bond pads to said plurality of conductive leads. 31.The packaged integrated circuit in claim 30, wherein said plurality ofdiscontiguous memory banks further comprises a plurality of partiallydiscontiguous memory banks.
 32. The packaged integrated circuit in claim31, said plurality of partially discontiguous memory banks furthercomprises a plurality of intervally continuous memory banks.
 33. Thepackaged integrated circuit in claim 32, wherein said plurality ofintervally continuous memory banks comprises two sub-arrays from onememory bank physically separated by at least one sub-array of at leastone other memory bank.
 34. The packaged integrated circuit in claim 30,wherein said plurality of discontiguous memory banks comprises twosequential sub-arrays from one memory bank physically separated by atleast one sub-array from at least one other memory bank.
 35. Thepackaged integrated circuit in claim 30, wherein said plurality ofdiscontiguous memory banks comprises two sub-arrays from one memory bankphysically separated by one sub-array from every other memory bank.